High voltage current switch circuit

ABSTRACT

The present invention relates to a high voltage switch circuit, comprising an input port adapted to receive a pulse type input current and an output port, which can be used selectively to conduct an output current to a corresponding electrical load. The switch circuit comprises a buffer stage adapted to sense the input voltage at said input port and to provide a buffered voltage that follows said input voltage. The switch circuit comprises complementary switches electrically connected between said input port and said output port and a voltage level translator electrically connected with said switches, said buffer stage and a control terminal that provides a control signal. The voltage level translator provides suitable gate voltages at the gate terminals of said switches, so that the operation of these latter can be controlled by said control signal.

The present invention relates to an electronic circuit of analog type, which can be of integrated type or realized with discrete components.

In particular, the present invention relates to a high voltage switch circuit for switching current signals, namely pulse type current signals, between an input port and a selectable output port.

In many applications, for example in the biomedical sector, multiplexers are used when it is necessary to supply a desired current signal to an output port, which can be activated selectively.

Italian patent application nr. MI2007A000595 describes a high voltage pulsed current generation circuit for a neuromuscular electrical stimulator. This document shows the use of a multiplexer having an input port adapted to receive a pulse type current signal, generated by a stimulation circuit, and a plurality of output ports, each of which can be selected to provide said current signal to a corresponding pair of stimulation electrodes.

Multiplexers, substantially of a type similar to the one described above, can also be used in biomedical applications of different type, such as in ultrasonic scanning apparatus.

Often, these devices do not have satisfactory galvanic isolation to ground of the output ports. In many devices, even if intended for use, for example, in biomedical applications, in which the presence of effective galvanic isolation is a very important design requirement, it is possible to encounter the presence of non-negligible leakage currents to ground. The intensity of said leakage currents increases, generally not linearly, with the voltage at the terminals of the input/output port.

Many prior art multiplexers have high power consumption, both in stand-by mode and during operation, which increases significantly if high voltages are present at the terminals of the input/output ports.

Another example of electronic stimulation device is disclosed in U.S. Pat. No. 5,052,391.

In this document, an electronic circuit to provide high voltage, high rise-time, and charge balanced current pulses is disclosed.

This electronic circuit does not actually have current multiplexing functionalities but it basically provides for the splitting of one output for a parallel connection with a plurality of output channels.

Moreover, such a circuit shows relevant drawbacks in terms of weight and size, since multiple transformers have to be used to transfer the energy of a stimulation pulse to the corresponding output channels. The overall bulkness of such a system makes it difficult to use in portable stimulators.

Further, the output current supplied to each output port is often subject to relevant waveform distortions due to the currents adsorbed by the adopted switching devices.

The main object of the present invention is to provide a switch circuit, which is capable of overcoming the drawbacks described above.

A further object of the present invention is to provide a switch circuit that can be controlled by logic type signals to switch an input current towards a selectable output port.

A further object of the present invention is to provide a switch circuit, in which input and output terminals have high impedance to ground for voltages within the specification ranges.

A further object of the present invention is to provide a switch circuit having low quiescent and active power consumption for voltages within the specification ranges.

A further object of the present invention is to provide a switch circuit that can be supplied by high voltage power supplies.

A further object of the present invention is to provide a switch circuit that is easy to produce at industrial level, as an integrated circuit or as a discrete component circuit, at competitive costs with respect to prior art devices.

These objects, together with other objects that will be more apparent from the subsequent description and from the accompanying drawings, are achieved, according to the invention, by a high voltage switch circuit according to claim 1, proposed hereafter, and the related dependent claims which refer to preferred embodiments of the present invention.

Further characteristics and advantages of the present invention will be more apparent with reference to the description given below and to the accompanying figures, provided purely for explanatory and non-limiting purposes, wherein:

FIG. 1A, 1B illustrate block diagrams showing the general operation and structure of the high voltage switch circuit, according to the present invention;

FIG. 2 illustrates a block diagram of a multiplexer comprising the high voltage switch circuit, according to the present invention;

FIG. 3 illustrates a block diagram of the output stage included in an embodiment the high voltage switch circuit, according to the invention;

FIG. 4 schematically illustrates the buffer stage included in the high voltage switch circuit, according to the invention;

FIG. 5-6 illustrate in more details the circuit structure of the output stage of the high voltage switch circuit, in the embodiment shown in FIG. 3.

With reference to the aforesaid figures, the present invention relates to a high voltage switch circuit 1.

The high voltage switch circuit 1 is particularly adapted for use in a muscular or neuromuscular electrical stimulator and it will now be described with reference to such an implementation for simplicity of exposition.

However, this is not intended to limit in any way the scope of the present invention.

In fact, the switch circuit 1 can be used in different biomedical applications, for example in an ultrasonic devices, or in other types of devices in which it is necessary to selectively activate a plurality of current controlled ports, such as micro-electromechanical devices or systems (MEMS).

Referring to FIGS. 1A-1B, the switch circuit 1 comprises an input port IN adapted to receive an input current I_(IN).

The input current I_(IN) is predefined and is generated by a current generator circuit 500, electrically connected with a pair of terminals (positive and negative) IN⁺ and IN⁻ of the input port IN.

The input current I_(IN) has a pulse type waveform, preferably of unipolar type.

The switch circuit 1 comprises an output port O_(I) that can receive the input current I_(IN) and conduct an output current I_(LI) to a corresponding electrical load L.

The switch circuit 1 is capable of directing the input current I_(IN) to the output port O_(I), when this latter is selected to conduct the output current I_(LI) to the load L_(I).

An input voltage V_(IN) is present between the terminals IN⁺ and IN⁻ of the input port IN, which is a function of the input current I_(IN) and of the downstream equivalent impedance seen from the terminals of the input port IN.

The input voltage V_(IN) can assume high values, for example values of a few hundreds of volts in an electrical stimulator.

The switch circuit 1 comprises an electronic buffer stage BUF that is electrically connected to the input port IN.

The buffer stage BUF is adapted to sense the input voltage V_(IN), at the terminals IN⁺, IN⁻ of the input port IN, and to supply, at a buffer output BF, a buffered voltage V_(BUF), which follows the sensed input voltage V_(IN).

The switch circuit 1 comprises complementary switches T₁, T₂ that operate as current switches and are electrically connected between the input port IN and the output port O_(I).

The switch circuit 1 comprises a first control terminal K₁ for providing a first control signal C₁ of logic type (for example at 0V and 3.3V).

Preferably, the switch circuit 1 is operatively associated with an electronic control stage COM adapted to generate the control signal C₁ and send it to the control terminal K₁, connected thereto.

In some embodiments of the present invention, the control stage COM may be physically included in the switch circuit 1.

Preferably, the control stage COM may comprise a digital processing device, for example a microprocessor, or a shift register or another circuit of similar type.

The switch circuit 1 comprises a first voltage level translator A₁ that is electrically connected with the buffer stage BUF, with the switches T₁, T₂ and with the control terminal K₁.

The voltage level translator A₁ is adapted to provide a first and second gate voltage V_(P1), V_(P2) respectively at a first and second gate terminal G₁, G₂ of the first and second switch T₁, T₂ to control said switches through the control signal C₁.

Depending on the control signal C₁, the switches T₁, T₂ enable or disable the flow of the input current I_(IN) from the input port IN to the output port O_(I), thus providing or blocking a current path from the input port I_(IN) to the output port O_(I) for the input current I_(IN).

The connectivity between the input port IN and each output port O₁ is determined by the control signal C₁ that selects the output port O₁ to receive the input current I_(IN).

The output current provided by the switches T₁, T₂ is thus equal to (I_(IN)*C₁) where C₁ is a logic signal having logic values equal to 0 or 1.

The adoption of the voltage level translator A₁ for providing the gate voltages V_(P1), V_(P2) is quite advantageous since it allows to properly set the voltage across the gate-source junctions of the switches T₁, T₂ in order to make it possible to control (in particular to turn on) said switches through the control signal C₁. The switches T₁, T₂ are in fact transistors in which the voltage across the gate-source junction may vary, since they have the source terminals electrically connected with the terminals of the input port IN.

As shown in FIGS. 1B and 3, the switches T₁, T₂, the voltage level translator A₁ and the input terminal K₁ form an output circuit NET₁ that is comprised in an electronic output stage M_(I) of the switch circuit 1.

The output stage M_(I) is electrically connected to the input port IN, the buffer stage BUF, the output port O_(I) and preferably to the control stage COM.

According to a preferred embodiment of the present invention (FIG. 4), the buffer stage BUF comprises a circuit structure divided into two sections, substantially symmetrical with respect to ground.

Each of the aforesaid sections comprises a sensing circuit B₁, B₂ arranged in such a manner as to sense the voltage of a corresponding terminal IN⁺, IN⁻ of the input port IN, and a voltage follower circuit F₁, F₂, arranged in such a manner that the voltage of the positive and negative terminals BF⁺, BF⁻ of the buffer output BF follow the sensed voltage.

This solution makes it possible to maintain a high impedance to ground for the input port IN and the buffer output BF, the voltages at the terminals of which are floating with respect to ground.

The buffer output BF provides, between the terminals BF⁺, BF⁻, the buffered voltage V_(BUF) that follows the variations of the voltage V_(IN) at the terminals IN⁺, IN⁻ of the input port IN.

This makes it possible to power the voltage level translator A₁ with high voltages (V_(PP) and V_(NN)) that are different from V_(IN), thereby without introducing significant distortions (for example due to unwanted current absorptions) in the input current I_(IN), when this latter flows toward the output port O_(I).

In a first section, the buffer stage BUF preferably comprises a first sensing circuit B₁ and a first follower circuit F₁.

Preferably, the sensing circuit B₁ is electrically connected with the positive terminal IN⁺ of the input port IN, with the sensing node S₁ and with a first power supply V_(CC).

The sensing circuit B₁ senses the voltage of the positive terminal IN⁺ of the input port IN and establishes an offset with respect to this voltage to compensate the threshold gate-source voltage of a transistor T₉ of the voltage follower circuit F₁ and prevent an unwanted conduction of the switch T₁.

Preferably, the sensing circuit B₁ comprises a Zener diode D₂₁ and a capacitor Z₂₁, connected in parallel between the positive terminal IN⁺ and the sensing node S₁.

The diode D₂₁ advantageously prevents from over-voltages at the sensing node S₁ while the capacitor Z₂₁ maintains the voltage offset with respect to the voltage of the positive terminal IN⁺.

Preferably, the sensing circuit B₁ comprises a resistor R₂₁ and a diode D₂₄ electrically connected in series between the power supply V_(CC) and the sensing node S₁.

The voltage follower circuit F₁ is electrically connected with the sensing node S₁, with the positive terminal BF⁺ of the buffer output BF and with a second power supply V_(PP), which is a high voltage power supply.

In the voltage follower circuit F₁, the voltage of the positive terminal BF⁺ substantially follows the voltage of the positive terminal IN⁺.

Preferably, the voltage follower circuit F₁ comprises the transistor T₉, for example an n-type enhancement mode MOSFET, connected between the power supply V_(PP) and ground through the resistor R₂₃.

The transistor T₉ has the gate terminal connected with the sensing node S₁, the drain terminal connected with the power supply V_(PP) and the source terminal connected with the terminal BF⁺ and to a resistor R₂₃, in turn connected with ground.

Operation of the first section of the stage BUF is now described in greater detail.

When there is no current flow towards the load L_(I) (e.g. the input current I_(IN) has no current pulses) the sensing node S₁ is at a voltage approximately equal to V_(CC).

The voltage of the terminal BF⁺ is therefore approximately equal to V_(IN) minus the voltage drop on the network composed of the circuit elements D₂₁, Z₂₁, D₂₄ and R₂₁ and the voltage V_(GSth)(T9), i.e. the threshold gate-source voltage of the transistor T₉.

The voltage of the sensing node S₁ follows the voltage of the terminal IN⁺, so that the voltage of the terminal BF⁺ follows the voltage of the terminal IN⁺ and the switch T₁ is in an OFF state.

If there is a current flowing toward the load L_(I) (i.e. the switch T₁ is in an ON state), the voltage of the terminal IN⁺ depends substantially on the voltage drop across said load. In this case, the voltage variations at the terminal IN⁺ are sensed by the sensing circuit B₁ and followed by the voltage at the terminal BF⁺.

A second section of the buffer stage BUF preferably has a circuit structure substantially symmetrical to that of the first section described above, which comprises a second sensing circuit B₂ and a second follower circuit F₂.

Preferably, the sensing circuit B₂ is electrically connected with the negative terminal IN⁻ of the input port IN, with a second sensing node S₂ and with a third power supply V_(DD).

The sensing circuit B₂ senses the voltage of the negative terminal IN⁻ of the input port IN and establishes a voltage offset with respect thereto to compensate the threshold gate-source voltage of a transistor T₁₀ of the voltage follower circuit F₂ and prevent an unwanted conduction of the switch T₂.

Preferably, the sensing circuit B₂ comprises a Zener diode D₂₂ and a capacitor Z₂₂, connected in parallel between the negative terminal IN⁻ and the sensing node S₂.

The diode D₂₂ advantageously prevents from over-voltages at the sensing node S₂ while the capacitor Z₂₂ maintains the voltage offset with respect to the voltage of the negative terminal IN⁻.

Preferably, the sensing circuit B₂ comprises a resistor R₂₆, and a diode D₂₃ electrically connected in series between the power supply V_(DD) and the sensing node S₂.

The follower circuit F₂ is electrically connected with the sensing node S₂ and with the negative terminal BF⁻ of the buffer output BF.

In the follower circuit F₂, the voltage of the negative terminal BF⁻ substantially follows the voltage of the negative terminal IN⁻.

Preferably, the follower circuit F₂ comprises the transistor T₁₀, for example a p-type enhancement mode MOSFET, connected between a fourth power supply V_(NN), which is a high voltage power supply, and ground through the resistor R₂₄.

In the transistor T₁₀, the gate terminal is connected with the sensing node S₂, the drain terminal is connected with the power supply voltage V_(NN) and the source terminal of the transistor T₁₀ is electrically connected with the terminal BF⁻ and to a resistor R₂₄, in turn connected with ground.

Operation of the second section of the stage BUF is substantially similar to that of the first section.

When there is no current flow toward the load L_(I) (e.g. the input current I_(IN) does not have current pulses), the sensing node S₂ is at a voltage approximately equal to V_(DD).

The voltage of the terminal BF⁻ is therefore approximately equal to V_(IN) minus the voltage drop on the network composed of the circuit elements D₂₂, Z₂₂, D₂₃ and R₂₆ and the voltage V_(GSth)(T10), i.e. the threshold gate-source voltage of the transistor T₁₀.

The voltage of the sensing node S₂ follows the voltage of the terminal IN⁻, so that the voltage of the terminal BF⁻ follows the voltage of the terminal IN⁻ and the switch T₂ is in OFF state.

If there is current flow toward the load L_(I) (i.e. the switch T₂ is in ON state), the voltage of the terminal IN⁻ depends substantially on the voltage drop across said load.

In this case, the voltage variations at the terminal IN⁻ are sensed by the sensing circuit B₂ and followed by the voltage at the terminal BF⁻.

The buffer stage BUF is thus capable to supply a buffered voltage V_(BUF) that follows the input voltage V_(IN) with a small power consumption and negligible distortions of the input current I_(IN).

The structure of the first output circuit NET_(T), in a preferred embodiment of the switch circuit 1 of the present invention (FIGS. 3 and 5), is now described in greater detail.

As mentioned above, the output circuit NET_(T) comprises the switches T₁, T₂, the voltage level translator A₁ and the control terminal K₁.

Preferably, the output circuit NET_(T) comprises a first output Y₁ electrically connected with the output port O_(I).

The first output Y₁ comprises a pair of terminals (positive and negative) Y₁ ⁺, Y₁ ⁻ electrically connected with a pair of terminals (positive and negative) O_(I) ⁺, O_(I) ⁻ the output port O_(I).

As shown in FIG. 3, the output Y₁ is electrically connected with the output port O_(I) in such a manner that the output current I_(LI), which is supplied by the output port O_(I) to the corresponding electrical load L_(I), has a waveform with the same polarity as the input current I_(IN).

In this case, the terminals Y₁ ⁺, Y₁ ⁻ of the output Y₁ are electrically connected with the terminals O_(I) ⁺, O_(I) ⁻ the output port O_(I) with direct polarity, i.e. with the positive terminal Y₁ ⁺ electrically connected with the positive terminal O_(I) ⁺ and the negative terminal Y₁ ⁻ electrically connected with the negative terminal O_(I) ⁺ the output port O_(I).

Of course, the output Y₁ may be electrically connected with the output port O_(I) in such a manner that the output current I_(LI) has a waveform with reversed polarity with respect to the input current I_(IN).

The switch T₁ is electrically connected between the positive terminal IN⁺ of the input port I_(IN) and the positive terminal Y₁ ⁺ of the output Y₁ and the switch T₂ is electrically connected between the negative terminal IN⁻ of the input port I_(IN) and the negative terminal Y₁ ⁻ of the output Y₁.

The switches T₁ and T₂ are complementary and are preferably field effect transistors (J-FETs or MOSFET), respectively of p- and n-enhancement mode type.

Advantageously, the transistors T₁ and T₂ are arranged to have the drain terminals electrically connected with the terminals Y₁ ⁺ and Y₁ ⁻ and the source terminals electrically connected with the terminals IN⁺ and IN⁻, respectively.

In this way, when the transistors T₁ and T₂ are in conduction state (switches T₁ and T₂ in ON state), the input current I_(IN) can flow from the terminals of the input port IN to the terminals of the output Y₁.

Instead, when the two transistors T₁ and T₂ are in cut-off state (switches T₁ and T₂ in OFF state), the passing of the input current I_(IN) toward the output Y₁ is prevented.

As mentioned above, the voltage level translator A₁ is advantageously adapted to control the switches T₁ and T₂ through the control signal C₁.

The voltage level translator A₁ is electrically connected between the terminals (positive and negative) BF⁺, BF⁻ of the buffer output BF and with the gate terminals G₁, G₂ of the switches T₁ and T₂.

The voltage level translator A₁ comprises a first polarization circuit including the circuit series of the resistor R₁, the third transistor T₃, the resistor R₂, the fourth transistor T₄ and the resistor R₃.

The transistors T₃, T₄ are preferably bipolar junction transistors (BJT), respectively of npn and pnp type, and are adapted to enable/prevent flow of a first polarization current I_(P1) along said first polarization circuit.

The transistors T₃, T₄ are arranged in such a manner to be controlled by the terminal K₁, according to the state of the control signal C₁.

Preferably, the transistor T₃ has its collector terminal electrically connected with the resistor R₁, which is in turn connected in series with the positive terminal BF⁺ of the buffer output BF, and is connected with the control terminal K₁, at the base terminal thereof.

Instead, the transistor T₄ has the base terminal connected to ground and the collector terminal electrically connected with the resistor R₃, which is in turn connected in series with the negative terminal BF⁻ of the buffer output BF.

The transistors T₃ and T₄ have their emitter terminals connected with the terminals of the resistor R₂.

As an alternative, the transistors T₃, T₄ may have their base terminals connected to the ground and to the terminal K₁, respectively.

Preferably, the voltage level translator A₁ comprises a first circuit network to protect the switches T₁ and T₂ (in particular their gate terminals G₁, G₂) against over-voltages.

This protective network advantageously comprises first and second over-voltage protection elements D₁ and D₂ (preferably Zener diodes) that are respectively connected between the gate terminals G₁, G₂ of the transistors T₁ and T₂ and the terminals IN⁺ and IN⁻ of the input port IN.

Preferably, the voltage level translator A₁ also comprises some stabilizing circuit elements, such as the resistor R₅ and the capacitor Z₁, connected in parallel with the resistor R₂, and the protection resistor R₄ and R₆, connected in series with the base terminals of the transistor T₃ and T₄, respectively.

Operation of the output circuit NET₁ is now described in greater detail.

Let us assume that the output circuit NET₁ is initially in a deactivated or stand-by state and the terminal K₁ receives a control signal C₁ at “low” logic level.

The transistors T₃ and T₄ are in the cut-off state and there is no flow of the polarization current I_(P1).

If the input current I_(IN) does not have any current pulses, the voltage at the terminal BF⁺ is approximately V_(CC)-V_(GS)(T₉) while the voltage at the terminal BF⁻ is approximately V_(DD)-V_(GS)(T₁₀), where V_(GS)(T₉) and V_(GS)(T₁₀) are the gate-source voltages of the transistors T₉ and T₁₀, respectively.

If the input current I_(IN) has a current pulse, the voltage at the terminals BF⁺ and BF⁻ increases up to V_(PP) and V_(NN) respectively.

In both cases, as there is no flow of the polarization current I_(P1), the voltage level translator A₁ provides gate voltages V_(P1), V_(P2) to the gate terminals G₁, G₂, such as to maintain the switches T₁ and T₂ in the cut-off state.

From the above, it is evident how, with a control signal C₁ at a “low” logic level, whatever the voltage V_(IN) and the input current I_(IN) (within the specification range of the circuit), the switches T₁ and T₂ remain in the OFF state and the input current I_(IN) cannot flow toward the output Y₁.

The output circuit NET₁ is therefore maintained in deactivated or stand-by state.

When the terminal K₁ receives a control signal C₁ at “high” logic level, the transistors T₃ and T₄ are taken to conduction state and the polarization current I_(P1) can flow.

In this situation, before the switching of the transistors T₃, T₄ is completed, the voltage at the terminals BF⁺ and BF⁻ initially tends to increase up to V_(PP) and V_(NN) respectively.

Due to the voltage drop across the resistors R₁ and R₃, which is determined by flow of the current I_(P1), the voltage level translator A₁ provides gate voltages V_(P1), V_(P2) to the gate terminals G₁, G₂, such as to take the switches T₁ and T₂ to the conduction state (ON state).

The switches T₁ and T₂ are taken to the ON state and the input current I_(IN) is free to flow toward the output Y₁.

At this point, the voltage at the terminals BF⁺ and BF⁻ depends substantially on the voltage across the load L_(I) but the voltage drop across the resistors R₁ and R₃, due to flow of the current I_(P1), ensures that the gate terminals G₁, G₂ are always at voltages such as to maintain the switches T₁ and T₂ in conduction state.

Therefore, with a control signal C₁ at a high logic level, whatever the voltage V_(IN) and the input current I_(IN) (within the specification range of the circuit), the switches T₁ and T₂ are always in ON state and the input current I_(IN) can flow toward the output Y₁.

From the above, it is apparent that the voltage level translator A₁ provides a voltage level shifting of the control signal C₁ to safely control the switches T₁, T₂, despite of the variations of the input voltage V_(IN), since these latter are constantly followed by the buffered voltage V_(BUF).

Given that the terminals of the output Y₁ are preferably connected with direct polarity to the terminals of the output port O_(I), the output current I_(IL) supplied to the electrical load L_(I), has a waveform with the same polarity as the input current I_(IN).

In other words, the condition IL_(I)=I_(IN) is obtained.

In this way, when the output circuit NET₁ is enabled by the control signal C₁ to transmit an input current I_(IN) of pulse type toward the output port O_(I), the output current I_(IL) has pulses with the same polarity and amplitude as the pulses of the input current I_(IN).

When the terminal K₁ again receives a control signal C₁ at “low” logic level, the transistors T₃ and T₄ return to the cutoff state and ideally there should be no flow of the polarization current I_(P1).

In this situation, in fact, the voltage level translator A₁ supplies, respectively to the gate terminals G₁, G₂ voltages V_(P1), V_(P2) such as to take the transistors T₁ and T₂ to cut-off state (OFF state).

Regardless of this, due to the presence of stray capacitances between the gate terminals G₁, G₂ and the terminal IN⁺ of the input port IN, the transistors T₁, T₂ do not switch immediately but are taken to OFF state only when the input current I_(IN) reaches zero, i.e. at the end of the input current pulse.

Based on the above, it can be observed that:

-   -   activation of the output circuit NET₁ is determined simply by         the transition of the control signal C₁ from a “low” logic level         to a “high” logic level;     -   deactivation of the output circuit NET₁ is instead determined by         transition of the control signal C₁ to “low” logic level and by         passage of the input current I_(IN) through zero.

It is therefore evident how the output circuit NET₁ behaves, from a functional viewpoint, in a manner substantially similar to that of a DIAC electronic device.

In an embodiment of the present invention, particularly suitable for use in a muscular or neuromuscular electrical stimulator, the switch circuit 1 comprises the fifth and sixth complementary switches T₅, T₆ that operate as current switches and that are electrically connected between the input port IN and the output port O_(I), in parallel with the switches T₁, T₂.

The switch circuit 1 comprises a second control terminal K₂ for providing a second control signal C₂ of logic type.

Preferably, the second control signal C₂ is received from the control stage COM.

The switch circuit 1 comprises a second voltage level translator A₃ that is electrically connected with the buffer stage BUF, with the switches T₅, T₆ and with the control terminal K₂.

The voltage level translator A₂ is adapted to provide a third and fourth gate voltage V_(P3), V_(P4) respectively at a third and fourth gate terminal G₃, G₄ of the switches T₅, T₆ in order to control these latter through the control signal C₂.

Depending on the control signal C₂, the switches T₅, T₆ can enable or disable the flow of the input current I_(IN) from the input port IN to the output port O_(I), thereby providing or blocking a current path from the input port I_(IN) towards the output port O_(I) for the input current I_(IN).

The connectivity between the input port IN and each output port O_(I) is determined by the control signal C₂ and the output current provided by the switches T₅, T₆ is thus equal to (I_(IN)*C₂), where C₂ is a logic signal having logic values equal to 0 or 1.

The adoption of the voltage level translator A₃ for providing the gate voltages V_(P3), V_(P4) is quite advantageous since it allows to properly set the voltage across the gate-source junction of the switches T₅, T₆ in order to make it possible to control (in particular to turn on) them through the control signal C₂.

As shown in FIGS. 3 and 6, the switches T₅, T₆, the voltage level translator A₃ and the control terminal K₂ form an output circuit NET₂, which is comprised in an output stage M_(I) of the switch circuit 1 and which is connected between the input port IN and the output port O_(I), as the output circuit NET₁.

Referring to FIG. 6, the output circuit NET₂ has a circuit structure similar to that of the circuit NET₁, described above.

The output circuit NET₂ comprises a second output Y₂ electrically connected with the output port O_(I).

The second output Y₂ comprises a pair of terminals (positive and negative) Y₂ ⁺, Y₂ ⁻ electrically connected with the terminals O_(I) ⁺, O_(I) ⁻ the output port O_(I).

Preferably, the output circuit NET₂ is electrically connected with the output port O_(I) in such a manner that the output current I_(LI), which is supplied by the output port O_(I) to the corresponding electrical load L_(I), has a waveform with reverse polarity with respect to that of the input current I_(IN).

In this case, the terminals Y₂ ⁺, Y₂ ⁻ of the output Y₂ are electrically connected with the terminals O_(I) ⁺, O_(I) ⁻ the output port O_(I) with reverse polarity, i.e. with the positive terminal Y₂ ⁺ electrically connected with the negative terminal O_(I) ⁻ and the negative terminal Y₂ ⁻ electrically connected with the positive terminal O_(I) ⁺ of the output port O_(I).

Of course, the output circuit NET₂ may be electrically connected with the output port O_(I) in such a manner that the output current I_(LI) has a waveform with direct polarity with respect to the input current I_(IN).

The switch T₅ is electrically connected between the positive terminal IN⁺ of the input port I_(IN) and the positive terminal Y₂ ⁺ of the output Y₂ and the switch T₆ is electrically connected between the negative terminal IN⁻ of the input port I_(IN) and the negative terminal Y₂ ⁻ of the output Y₂.

The switches T₅ and T₆ are complementary and preferably field effect transistors (FET or MOSFET), respectively of p- and n-port enhancement mode type.

Advantageously, the switches T₅ and T₆ are arranged in such a manner as to have the drain terminals electrically connected with the terminals Y₂ ⁺ and Y₂ ⁻ and the source terminals electrically connected with the terminals IN⁺ and IN⁻, respectively.

In this way, when the transistors T₅ and T₆ are in conduction state (switches T₅ and T₆ in ON state), the input current I_(IN) can flow from the terminals of the input port IN to the terminals of the output Y₂.

Instead, when the transistors T₅ and T₆ are in the cut-off state (switches T₅ and T₆ in OFF state), the passage of the input current I_(IN) toward the output Y₂ is prevented.

Preferably, the voltage level translator A₃, adapted to control the transistors T₅ and T₆, is electrically connected between the terminals (positive and negative) BF⁺ and BF⁻ of the buffer output BF and with the gate terminals G₃, G₄ of the switches T₅ and T₆.

The voltage level translator A₃ advantageously comprises a second polarization circuit formed by the circuit series consisting of the resistor R₁₁, the seventh transistor T₇, the resistor R₁₂, the eighth transistor T₈ and the resistor R₁₃.

The transistors T₇ and T₈ are preferably bipolar junction transistors (BJT), respectively of npn and pnp type, and are adapted to enable/prevent flow of a second polarization current I_(P2) along said second polarization circuit.

Preferably, the transistor T₇ has its collector terminal electrically connected with the resistor R₁₁, in turn connected in series with the positive terminal BF⁺ of the buffer output BF, and is connected with the terminal K₂, at the base terminal thereof.

The transistor T₈ has the base terminal connected with ground and the collector terminal electrically connected with the resistor R₁₃, in turn connected in series with the negative terminal BF⁻ of the buffer output BF.

The transistors T₇ and T₈ have their emitter terminals connected to the terminals of the resistor R₁₂.

As an alternative, the transistors T₇, T₈ may have their base terminals connected to the ground and to the terminal K₂, respectively.

Preferably, the voltage level translator A₃ comprises a second circuit network to protect the gate terminals of the transistors T₅ and T₆ against over-voltages.

This protective network advantageously comprises third and fourth over-voltage protection elements D₁₀ and D₁₁ (preferably Zener diodes) that are respectively connected between the gate terminals G₃, G₄ of the transistors T₅ and T₆ and the terminals IN⁺ and IN⁻ of the input port IN.

Preferably, the voltage level translator A₃ also comprises some stabilizing circuit elements, such as the resistor R₁₅ and the capacitor Z₁₀, connected in parallel with the resistor R₁₂, and the protection resistor R₁₄ and R₁₆ connected in series with the base terminals of the transistors T₇ and T₈, respectively.

Operation of the output circuit NET₂ is similar to that of the output circuit NET₁.

Let us assume that the output circuit NET₂ is initially in a deactivated state and the terminal K₂ receives a logic control signal C₂ at “low” level. The transistors T₇ and T₈ are in the cut-off state and there is no flow of the polarization current I_(P2).

In this situation, in the presence or absence of pulses of the input current I_(IN), the gate terminals of the switches T₅ and T₆ are always at gate voltages V_(P3), V_(P4) such as to maintain them in a cut-off state.

Therefore, with a control signal C₂, at a low logic level, the switches T₅ and T₆ remain in the OFF state and the input current I_(IN) cannot in any case flow toward the output Y₂.

The output circuit NET₂ is therefore maintained in a deactivated or stand-by state.

When the terminal K₂ receives a logic control signal C₂ at “high” level, the transistors T₇ and T₈ switch to conduction state and the polarization current I_(P2) can flow.

In this situation, due to the voltage drop across the resistors R₁₁ and R₁₃, determined by the flow of the current I_(P2), the gate terminals G₃, G₄ of the transistors T₅ and T₆ are polarized at gate voltages V_(P3), V_(P4) such as to take the transistors T₅ and T₆ to conduction state.

The switches T₅ and T₆ are then taken to the ON state and the input current I_(IN) is free to flow toward the output Y₂.

At this point, the voltage at the terminals BF⁺ and BF⁻ depends substantially on the voltage across the load L_(I) but the voltage drop across the resistors R₁₁ and R₁₃, due to circulation of the current I_(P2), ensures that the gate terminals G₃, G₄ are always at gate voltages V_(P3), V_(P4) such as to maintain the transistors T₅ and T₆ in conduction state.

Therefore, with a control signal C₂ at high logic level, whatever the voltage V_(IN) and the input current I_(IN) (within the specification range of the circuit), the switches T₅ and T₆ are always in the ON state and the input current I_(IN) can in any case flow toward the output Y₂.

From the above, it is apparent that the voltage level translator A₃ provides a voltage level shifting of the control signal C₃ to safely control the switches T₅, T₆, despite of the variations of the input voltage V_(IN), since these latter are constantly followed by the buffered voltage V_(BUF).

Given that the terminals of the output Y₂ are preferably connected with reverse polarity to the terminals of the output port O_(I), the output current I_(IL) supplied to the electrical load L_(I), will have a waveform with reverse polarity with respect to the input current I_(IN).

In other words, the condition IL_(I)=−I_(IN) is obtained.

In this way, when the output circuit NET₂ is enabled by the control signal C₂ to transmit a pulse type input current I_(IN) toward the output port O_(I), the output current I_(IL) has pulses with the same amplitude but with reverse polarity with respect to the pulses of the input current I_(IN).

When the terminal K₂ once again receives a control signal C₂ at “low” logic level, the transistors T₇ and T₈ are again taken to the cutoff state and ideally there should be no flow of the polarization current I_(P2).

In this situation, the voltage level translator A₃ supplies, respectively to the gate terminals of the transistors T₅ and T₆, gate voltages V_(P3), V_(P4) such as to take the same transistors T₅ and T₆ to the cut-off state.

Regardless of this, due to the presence of stray capacitances between the gate terminals of the transistors T₅, T₆ and the terminal IN⁻ of the input port, the transistors T₅, T₆ do not switch immediately but are taken to the cut-off state only when the input current I_(IN) reaches zero, i.e. at the end of the input current pulse.

On the basis of the above, it can be observed that:

-   -   activation of the output circuit NET₂ is determined simply by         transition of the control signal C₂ from a “low” logic level to         a “high” logic level;     -   deactivation of the output circuit NET₂ is determined by         transition of the control signal C₂ at “low” logic level and by         passage of the input current I_(IN) through zero.

Therefore, also the output circuit NET₂ behaves, from a functional viewpoint, in a manner substantially similar to that of a DIAC electronic device.

Referring to FIG. 2, the high voltage switch circuit 1, which does not have multiplexing functionalities per se, is particularly suitable for implementation in a multiplexer 100.

The multiplexer 100 comprises a common input port IN and a plurality of output ports O_(I), each of which can be selected by logic control signals.

The multiplexer 100 receives an input current I_(IN) at the input port IN and it directs it towards the selected output ports O_(I).

The multiplexer 100 thus implements a multiplexing function of the type 1→N, with N>1, for the current signals received at the input port IN.

The adoption of the high voltage switch circuit 1 in a multiplexer 100 is particularly advantageous for use in an electrical stimulator.

In this case, each of the mentioned output ports can be electrically connected with a pair of stimulation electrodes and the output current, supplied by each output port, is the current effectively injected by the electrodes during stimulation, while the electrical load connected to each output port typically consists of the impedance offered by the stimulation electrodes and by the portion of the patient's body affected by the stimulation current.

The multiplexer 100 comprises a common buffer stage BUF (as described above), which senses the voltage V_(IN) between the terminals of the input port IN and provides, at the buffer output BF, a buffered voltage V_(BUF) that substantially follows the input voltage V_(IN).

The multiplexer 100 comprises a plurality of output stages M_(I), each of which is electrically connected with the input port IN, the common buffer stage BUF and a corresponding output port O_(I).

Each of the output stages M_(I) comprises the output circuit NET₁ and preferably also the output circuit NET₂, as described above.

Preferably, the control terminals K₁ (and possibly K₂) of each output stage M_(I) are electrically connected with a common control stage COM that may be physically included in the multiplexer 1.

It is apparent that the common buffer stage BUF and each of the output stages M_(I) form a switch circuit 1, according to the invention, which is electrically connected between the input port IN and the corresponding output port O_(I) (FIG. 2).

The operation of the multiplexer 100 is now briefly described.

Normally, the output stages M_(I) are maintained in a deactivated state.

Therefore, the control signals sent by the control stage COM are normally maintained at a “low” logic level.

To direct the input current I_(IN) toward any desired output port O_(I), the control stage COM must activate the output circuit NET₁ (or optionally the output circuit NET₂) of the output stage M_(I), which is operatively associated with the chosen output port O_(I).

The control signal C₁ (or possibly C₂) sent to the output circuit NET₁ (or possibly NET₂) of the output stage M_(I), is therefore taken to “high” logic level, enabling the input current I_(IN) to flow toward the output port O_(I).

If the output Y₁ (or possibly Y₂) of the output circuit NET₁ (or NET₂) is connected with direct polarity to the output port O_(I), the output current I_(IL) has the same waveform as the input current I_(IN).

If the output Y₁ (or possibly Y₂) of the output circuit NET₁ (or NET₂) is connected with reverse polarity to the output port O_(I), the output current I_(IL) has a waveform with pulses of opposite polarity with respect to the input current I_(IN).

It can be noted how by suitably managing the output circuit NET₁ (or NET), one or more pulses of the input current I_(IN) can be “neutralized”, simply by maintaining the control signals C₁ (or C₂) in the “low” logic state. The pulses of the input current I_(IN) thus “neutralized”, do not appear, with direct or reverse polarity, in the output current I_(IL).

In this case, the output current I_(IL) has a different time distribution of the pulses, with respect to the input current I_(IN).

Operation of the output stage M_(I), as adjusted by the control signals C₁, C₂, can be summarized in the following exemplificative table:

C₁ C₂ M_(I) I_(LI) 0 0 OFF 0 0 1 Circuit NET₂ ON (reversing) −I_(IN) 1 0 Circuit NET₁ ON (not reversing) I_(IN) 1 1 Short circuit 0 (V_(IN=0))

From the table above it is evident how the output current from each output stage M_(I) is equal to (I_(IN)*C₁) or (I_(IN)*C₂), where C₁, C₂ are logic signals that assume the logic values 0 or 1.

The multiplexer 1 is therefore not only capable of reversing the polarity of the pulses of the input current I_(IN) (for example, by alternately activating the switching circuits NET₁ and NET₂₅ where both are present) but also of modifying the waveform of this latter.

The use of the switching circuits NET₁ and (optionally) NET₂ in each output stage M_(I), with the functionalities described above, is particularly useful in the case in which the multiplexer is used in a muscular or neuromuscular electrical stimulator.

For different biomedical applications or for other scopes of use of the multiplexer 1, the output stages M_(I) may however have different structure and functionality and comprise only the output circuit NET₁.

It has been seen in practice how the high voltage switch circuit 1, according to the present invention, allows the set objects to be achieved.

With respect to prior art devices, the switch circuit 1 has improved functionalities, in terms of reduction of dissipated power and high impedance of inputs/outputs.

The switch circuit 1 ensures effective high impedance of inputs and outputs. It is arranged in such a manner that the voltages present between the terminals of the input port IN, of any output port O_(I) and of the buffer output BF are virtually floating with respect to ground.

An advantage of the switch circuit 1 is the absence of working point bias currents for the active elements (transistors). This substantially reduces the power consumption to what is caused by leakage currents in the transistors.

Additional power consumption in active state is caused by charging/discharging of the parasitic capacitances trough the polarization currents I_(P1), I_(P2). This can be minimized through reducing the time periods during which the control signals C₁, C₂ are at a logic level commanding the ON state for the switches T₁, T₂, T₅, T₆. This is basically a design factor that depends on the parasitic capacitances, mainly in said switches.

The switch circuit 1 is particularly suitable for operating in the presence of high voltages to the terminals of the input port IN or of the output port.

For this purpose, it is sufficient to select in the most appropriate manner the type of transistor of each output stage.

The switch circuit 1 is characterized by considerable flexibility of use.

It is particularly suitable for use in biomedical applications, such as in a muscular or neuromuscular electrical stimulator.

In this application, the use of the output circuits NET₁ and NET₂ for the output stage M_(I), according to the description above, enables simple and effective adjustment of the polarity and time distribution of the output current I_(LI), at each output port O_(I).

However, the switch circuit 1 can be easily integrated in other biomedical applications, for example in ultrasonic devices or micro-electromechanical devices or systems (MEMS).

The switch circuit 1 has a simple structure and is easy and inexpensive to produce at industrial level, with manufacturing techniques using discrete or integrated components. 

1. A high voltage switch circuit (1) which comprises an input port (IN) and an output port (OI), a buffer stage (BUF) that is electrically connected with said input port, a first switch (T1) and a second switch (T2) operating as current switches, which are complementary and are electrically connected between said input port (IN) and said output port (OI), a first control terminal (K1) for providing a first control signal (C1), a first voltage level translator (A1) that is electrically connected with said buffer stage (BUF), with said first and second switch (T1, T2) and with said first control terminal (K1), said first voltage level translator providing a first and second gate voltage (VP1, VP2) at a first and second gate terminal (G1, G2) of said first and second switch (T1, T2) to control said first and second switch (T1, T2) through said first control signal (C1), said first and second switch, controlled by said first control signal (C1), enabling or disabling the flow of an input current (IIN) from said input port to said output port.
 2. The high voltage switch circuit, according to claim 1, wherein said first and second switch (T1, T2) are field effect transistors.
 3. The high voltage switch circuit, according to claim 1, wherein said first voltage level translator (A1) is electrically connected between a pair of terminals (BF+, BF−) of a buffer output (BF) of said buffer stage (BUF), said voltage level translator comprising a third transistor (T3) and a fourth transistor (T4) to provide said first and second gate voltage (VP1, VP2), said third and fourth transistor (T3, T4) being electrically connected with said first control terminal (K1) and to ground, respectively, or vice versa.
 4. The high voltage switch circuit, according to claim 1, wherein said first voltage level translator (A1) comprises a first over-voltage protection element (D1) that is electrically connected between the first gate terminal (G1) of said first switch (T1) and a positive terminal (IN+) of said input port (IN) and a second over-voltage protection element (D2) that is electrically connected between the second gate terminal (G2) of said second switch (T2) and a negative terminal (IN−) of said input port (IN).
 5. The high voltage switch circuit, according to claim 1, wherein said buffer stage (BUF) comprises: a first sensing circuit (B1), electrically connected with a positive terminal (IN+) of said input port (IN), with a first sensing node (S1) and with a first power supply (VCC), said first sensing circuit sensing the voltage of the positive terminal (IN+) of said input port (IN) and establishing a voltage offset with respect thereto; a first voltage follower circuit (F1), electrically connected with said first sensing node (S1), with a positive terminal (BF+) of the buffer output (BF) of said buffer stage (BUF) and with a high voltage second power supply (VPP), said first voltage follower circuit providing a voltage at the positive terminal (BF+) of the buffer output (BF), which follows the voltage of the positive terminal (IN+) of said input port (IN); a second sensing circuit (B2), electrically connected with a negative terminal (IN−) of said input port (IN), with a second sensing node (S2) and with a third power supply (VDD), said second sensing circuit sensing the voltage of the negative terminal (IN−) of said input port (IN) and establishing a voltage offset with respect thereto; a second voltage follower circuit (F2), electrically connected with said second sensing node (S2), with a negative terminal (BF−) of said buffer output (BF) and with a high voltage fourth power supply (VNN), said second voltage follower providing a voltage at the negative terminal (BF−) of the buffer output (BF), which follows the voltage of the negative terminal (IN−) of said input port (IN).
 6. The high voltage switch circuit, according to claim 1, wherein it is operatively associated with or it comprises a control stage (COM) that outputs said first control signal (C1).
 7. The high voltage switch circuit, according to claim 1, which comprises a fifth switch (T5) and a sixth switch (T6) operating as current switches, which are complementary and are electrically connected between said input port (IN) and said output port (OI), in parallel with respect to said first and second switch (T1, T2), a second control terminal (K2) for providing a second control signal (C2), a second voltage level translator (A3) that is electrically connected with said buffer stage (BUF), with said fifth and sixth switch (T5, T6) and with said second control terminal (K2), said second voltage level translator providing a third and fourth gate voltage (VP3, VP4) at a third and fourth gate terminal (G3, G4) of said fifth and sixth switch (T5, T6) to control said fifth and sixth switch (T5, T6) through said second control signal (C2), said fifth and sixth switch, controlled by said second control signal (C2), enabling or disabling the flow of an input current (IIN) from said input port to said output port.
 8. The high voltage switch circuit, according to claim 7, wherein said fifth and sixth switch are field effect transistors.
 9. The high voltage switch circuit, according to claim 7, which comprises a first output (Y1) that is electrically connected with said first and second switch (T1, T2) and a second output (Y2) that is electrically connected with said fifth and sixth switch (T5, T6), said first output (Y1) being electrically connected with said output port (OI) with a direct polarity and said second output (Y2) being electrically connected with said output port (OI) with an inverse polarity, or vice versa.
 10. The high voltage switch circuit, according to claim 7, wherein said second voltage level translator (A2) is electrically connected between a pair of terminals (BF+, BF−) of a buffer output (BF) of said buffer stage (BUF), said voltage level translator comprising a seventh transistor (T7) and a eighth transistor (T8) to provide said third and fourth gate voltage (VP3, VP4), said seventh and eighth transistor (T7, T8) being electrically connected with said second control terminal (K2) and to ground, respectively, or vice versa.
 11. The high voltage switch circuit, according to claim 7 wherein said second voltage level translator (A2) comprises a third over-voltage protection element (D10) that is electrically connected between the third gate terminal (G1) of said fifth switch (T5) and a positive terminal (IN+) of said input port (IN) and a fourth over-voltage protection element (D11) that is electrically connected between the fourth gate terminal (G4) of said sixth switch (T6) and a negative terminal (IN−) of said input port (IN).
 12. A high voltage current multiplexer (100) which comprises a high voltage switch circuit (1), according to claim
 1. 13. A muscular or neuromuscular electrical stimulator which comprises a high voltage switch circuit (1), according to claim
 1. 14. An ultrasonic device which comprises a high voltage switch circuit (1), according to claim
 1. 15. A micro-electromechanical device which comprises a high voltage switch circuit (1), according to claim
 1. 16. The high voltage switch circuit, according to claim 2, wherein said first voltage level translator (A1) is electrically connected between a pair of terminals (BF+, BF−) of a buffer output (BF) of said buffer stage (BUF), said voltage level translator comprising a third transistor (T3) and a fourth transistor (T4) to provide said first and second gate voltage (VP1, VP2), said third and fourth transistor (T3, T4) being electrically connected with said first control terminal (K1) and to ground, respectively, or vice versa.
 17. The high voltage switch circuit, according to claim 2, wherein said first voltage level translator (A1) comprises a first over-voltage protection element (D1) that is electrically connected between the first gate terminal (G1) of said first switch (T1) and a positive terminal (IN+) of said input port (IN) and a second over-voltage protection element (D2) that is electrically connected between the second gate terminal (G2) of said second switch (T2) and a negative terminal (IN−) of said input port (IN).
 18. The high voltage switch circuit, according to claim 3, wherein said first voltage level translator (A1) comprises a first over-voltage protection element (D1) that is electrically connected between the first gate terminal (G1) of said first switch (T1) and a positive terminal (IN+) of said input port (IN) and a second over-voltage protection element (D2) that is electrically connected between the second gate terminal (G2) of said second switch (T2) and a negative terminal (IN−) of said input port (IN).
 19. The high voltage switch circuit, according claim 2, wherein said buffer stage (BUF) comprises: a first sensing circuit (B1), electrically connected with a positive terminal (IN+) of said input port (IN), with a first sensing node (S1) and with a first power supply (VCC), said first sensing circuit sensing the voltage of the positive terminal (IN+) of said input port (IN) and establishing a voltage offset with respect thereto; a first voltage follower circuit (F1), electrically connected with said first sensing node (S1), with a positive terminal (BF+) of the buffer output (BF) of said buffer stage (BUF) and with a high voltage second power supply (VPP), said first voltage follower circuit providing a voltage at the positive terminal (BF+) of the buffer output (BF), which follows the voltage of the positive terminal (IN+) of said input port (IN); a second sensing circuit (B2), electrically connected with a negative terminal (IN−) of said input port (IN), with a second sensing node (S2) and with a third power supply (VDD), said second sensing circuit sensing the voltage of the negative terminal (IN−) of said input port (IN) and establishing a voltage offset with respect thereto; a second voltage follower circuit (F2), electrically connected with said second sensing node (S2), with a negative terminal (BF−) of said buffer output (BF) and with a high voltage fourth power supply (VNN), said second voltage follower providing a voltage at the negative terminal (BF−) of the buffer output (BF), which follows the voltage of the negative terminal (IN−) of said input port (IN).
 20. The high voltage switch circuit, according claim 3, wherein said buffer stage (BUF) comprises: a first sensing circuit (B1), electrically connected with a positive terminal (IN+) of said input port (IN), with a first sensing node (S1) and with a first power supply (VCC), said first sensing circuit sensing the voltage of the positive terminal (IN+) of said input port (IN) and establishing a voltage offset with respect thereto; a first voltage follower circuit (F1), electrically connected with said first sensing node (S1), with a positive terminal (BF+) of the buffer output (BF) of said buffer stage (BUF) and with a high voltage second power supply (VPP), said first voltage follower circuit providing a voltage at the positive terminal (BF+) of the buffer output (BF), which follows the voltage of the positive terminal (IN+) of said input port (IN); a second sensing circuit (B2), electrically connected with a negative terminal (IN−) of said input port (IN), with a second sensing node (S2) and with a third power supply (VDD), said second sensing circuit sensing the voltage of the negative terminal (IN−) of said input port (IN) and establishing a voltage offset with respect thereto; a second voltage follower circuit (F2), electrically connected with said second sensing node (S2), with a negative terminal (BF−) of said buffer output (BF) and with a high voltage fourth power supply (VNN), said second voltage follower providing a voltage at the negative terminal (BF−) of the buffer output (BF), which follows the voltage of the negative terminal (IN−) of said input port (IN). 